1. Field of the Invention
The present invention relates to a cache control device, and more particularly, to a cache control device having a function preventing a fault of a cache memory due to a soft error.
2. Discussion of Related Art
A cache memory is located between a processor and a main memory of a computer, and a memory operating at a high speed under the control of the processor. The cache memory has a smaller storage capacity than the main memory, and has a higher response speed than the main memory. Accordingly, data stored in the cache memory is accessed more quickly than data stored in the main memory.
A portion of data and instructions stored in the main memory may be stored in the cache memory. For example, the cache memory temporarily stores an instruction and data required by the processor together with, an address.
However, when an error is generated in the cache memory due to external factors and an erroneous instruction is read from the cache memory, the processor performs an operation of an unwanted program, or recognizes as an instruction which does not exist since the instruction read from the cache memory cannot be analyzed. Further, when erroneous data from the cache memory is read, the program generates an erroneous result due to the erroneous data.